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MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. The chip contains four inverters, one NOR gate and one NAND gate. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14572UBCP AWLYYWW 1 16 SOIC­16 D SUFFIX CASE 751B 1 16 SOEIAJ­16 F SUFFIX CASE 966 MC14572UB ALYW 1 14572U AWLYWW · · · · · · · · Diode Protection on All Inputs Single Supply Operation Supply Voltage Range = 3.0 Vdc to 18 Vdc NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter NOR Output Pin Adjacent to Inverter Input Pin For OR Application NAND Output Pin Adjacent to Inverter Input Pin For AND Application Capable of Driving Two Low­power TTL Loads or One Low­Power Schottky TTL Load over the Rated Temperature Range MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V mA A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION mW °C °C °C Device MC14572UBCP MC14572UBD MC14572UBDR2 MC14572UBF MC14572UBFEL Package PDIP­16 SOIC­16 SOIC­16 SOEIAJ­16 SOEIAJ­16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14572UB/D MC14572UB PIN ASSIGNMENT OUTA INA OUTB INB OUTC IN 1C IN 2C VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD IN 2F IN 1F OUTF INE OUTE IND OUTD LOGIC DIAGRAM 2 1 4 3 6 7 5 10 9 12 11 14 15 VDD = PIN 16 VSS = PIN 8 13 CIRCUIT SCHEMATIC VDD VDD VDD 2 1 7 13 14 6 VSS 5 VSS 15 VSS http://onsemi.com 2 MC14572UB ООООООООООООООО